1. Field of the Invention
This invention relates generally to the computer systems, and, more specifically, to a system and method for transferring information between processors.
2. Description of the Background Art
In a computer system, a primary processor may handle command execution and data manipulation by itself. However, when a specific type of command or data needs to be processed at high speeds, a generic multifunction primary processor can hand the job over to a specialized co-processor designed to process that specific type of command or data. For example, a graphics co-processor could efficiently handle all the graphics command and data for the slower more generalized primary processor. To give a specific task to a co-processor, the primary processor sends commands and corresponding data to the co-processor.
A specialized co-processor can often execute the commands faster than the primary processor can send the commands and corresponding data. Therefore, the amount of commands a co-processor is able to execute in a fixed period of time is frequently limited by the rate at which the primary processor is able to send commands and corresponding data to the co-processor.
A variety of methods are known for transferring commands and corresponding data from one processor to another. One such method for transferring this information is referred to as the "separate address, separate data" method, which will be abbreviated the "SASD method" for purposes of this application. In the SASD method, the data and command information transferred to the co-processor is accompanied by the address information specifying the registers in the co-processor to which data and commands are to be written. In the SASD method, some lines of the bus are dedicated to address information and some lines of the bus are dedicated to data and command information. In each bus cycle, data or command information travels across the bus in parallel with its corresponding destination register address. The receiving co-processor then writes the command and data information to the register specified by the user.
The speed of the information transfer in the SASD method is directly proportional to the width of the bus. More bus width means more address, command, and data information can transmitted in a bus cycle. Thus, in order to increase the rate at which information is transmitted, the bandwidth for both the address and the data/command information must be increased. However, increasing the bandwidth means increasing the number of input/output pins used for this transmission in both the processor and the co-processor. In other words, the number of pins on the processors directly limits the number of bus lines that can be used. Because the pins are one of the most expensive parts of the processor, adding speed by adding pins greatly increases the cost of the processor. Thus, increasing speed by increasing the bus bandwidth for the address and data/command information is not an economically desirable solution.
Another known method for transferring information across the bus is the alternate address/data (AAD) method, which alternates sending the address information and data/command information. For instance, for a 32 bit bus, 32 bits of address information will be sent on one bus cycle and a 32 bits of data and command information will be sent on the next bus cycle. In this method, address, data and command information share the same bus lines. For the same number of bus lines used, this method is not as fast as the SASD method because the data/command information and the address information alternate bus cycles. In general, this method is one half the speed of the SASD method for the same bus bandwidth.
A faster information transfer is achieved by transmitting information in a "burst" mode, such as the burst mode of the PCI bus developed by Intel Corporation. As in the AAD method described above, the address information and data/command information share the same bus lines in the burst mode.
In conventional burst modes, address information is sent only for the first piece of command or data information sent in a burst sequence. Address information does not accompany subsequent data and command information transmitted in the burst mode. In the conventional burst method, the co-processor assumes information transmitted should be stored at sequential memory addresses. Thus, after the co-processor stores the first bus cycle of information in one of its registers, it stores the data and command information arriving on each subsequent bus cycle at sequential memory addresses.
The advantage of the burst method over the SASD method is that, for the same speed performance, information can be transmitted without requiring as many bus lines as the SASD method. The advantage of the burst method over the AAD method is that the burst mode saves many bus cycles by only sending one bus cycle of address information, thereby increasing the transmission rate. Additionally, bus arbitration for information transmitted using either the SASD method or the AAD method is such that the information is subject to periodic delays, which slow down the transmission process. A burst sequence, however, is not subject to such delays.
The burst mode is typically used by the processor's cache controller for retrieving and storing only information at sequential memory addresses. The burst mode cannot typically be used to send command or control information to a co-processor. In order to send information to a co-processor in the burst mode, the information must be stored in sequential addresses and must be sent in the order of their sequential addresses. Command and control information is not typically stored in sequential addresses.
The fact that a conventional burst mode requires information to be stored in sequential memory addresses causes bus cycles to be wasted when information that is to be stored in non-sequential memory addresses is transferred in the burst mode. This is because more data than is required by the command often needs to be sent in order to maintain the order in which information is to be sent. For example, assume that the processor needs to send data to registers at addressed two, three and six in the co-processor. There are two ways to send the information such that the co-processor correctly writes the information into registers two, three, and six. One such way is to send the information in two burst sequences. The first burst sequence would have the address and data information for register two, as well as the data for register three. The second burst sequence would have the address and data information for register six. The disadvantages with this way are that there may be a delay between each burst sequence (due to bus arbitration) and that the address information for registers two and six has to be sent.
The other way is to send the information in one burst sequence. In order for the co-processor to correctly write the information into registers two, three, and six with this way, the information for registers 2-6 must be sent. FIG. 1a illustrates an example of the contents of the registers having addresses 1-6 and the contents of bus cycles 1-7 where the information is sent in on bus sequence. The first piece of information transmitted is the register address, 2, at which the first piece of data is to be stored. Next the data "O," which is to be written in register 2, is sent on bus cycle 2. Because the transmission is in the burst mode, the address of the next piece of data, "L," need not be sent. Instead, the next address (three) is determined by increasing the previous address by 1, and, therefore "L" is stored in register 3. A bus cycle is wasted sending data to register four because new data does not need to be sent to register 4. Either the data "U" already stored in register four must be re-sent or data indicating no change ("x") must be sent. Another bus cycle is also wasted sending information to register 5 because no new data needs to be sent to register 5. Thus, either the data, "T" already stored in register 5 must be sent, or data indicating no-change ("x") must be sent.
On bus cycle 6, the data, "I" to be stored in register 6 is sent, thereby completing the transfer. Note that if data had not been sent for registers four and five, the data, "I" for register 6 would have been stored in register 4 because incoming data is stored at consecutive addresses.
Therefore, in view of these disadvantages, it is desirable to have a system and method for transferring information in the burst mode without requiring that the data and command information be stored at sequential addresses and without wasting bus cycles on unnecessary data or commands.